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september 2013 doc id 7214 rev 10 1/19 1 l9826 octal protected low-side driver with diagnostic and serial/parallel input control features 8 channels low side driver with 450 ma output current capability typical r dson 1.5 ? at t j = 25 c parallel control fo r output 1 and 2 spi control on all outputs reset function diagnostic through 8 bit spi intrinsic output voltage clamping 50 v (typ) protection for inductive load drive short circuit current limitation and thermal shutdown for outputs 1 and 2 overcurrent and short circuit shutdown for outputs 3 to 8 description the l9826 is a protected octal low-side driver ic designed for the automotive environment. the 8 -bit serial peripheral interface (spi) is able to control the device's eight channels and to provide its load's diagnosis. in addition output 1 and 2 can also be controlled through dedicated input pins non1 and non2. overcurrent and short-circuit protections are present as well as the output voltage clamping which is able to protect the l9826 during operation with inductive loads. so20 '!0'03 table 1. device summary order code package packing l9826 so20 tube l9826tr so20 tape and reel e-l9826 so20 tube E-L9826TR so20 tape and reel www.st.com
contents l9826 2/19 doc id 7214 rev 10 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.1 via parallel, only for output 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.2 via 8-bit spi for all the outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 output stage diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3.1 diagnostic on outputs 1 and 2 controlled via non1/non2 . . . . . . . . . 15 5.3.2 diagnostic on outputs 1 to 8 controlled via spi . . . . . . . . . . . . . . . . . . 15 5.4 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.1 flyback current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.2 current regulation mode outputs 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.3 short circuits outputs 3 to 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
l9826 list of tables doc id 7214 rev 10 3/19 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings for voltages and currents applied externally to the device. . . . . 7 table 4. absolute maximum ratings for currents determined within the device . . . . . . . . . . . . . . . . . 7 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 6. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7. outputs control tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. diagnostic table for outputs 1 and 2 in parallel controlled mode . . . . . . . . . . . . . . . . . . . . 15 table 9. diagnostic table for outputs 1 to 8 in spi controlled mode . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
list of figures l9826 4/19 doc id 7214 rev 10 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. typical application circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. parallel control for output 1 and 2 (example for power-on) . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. output control register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. timing of the serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. the pulse diagram to read the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. the structure of the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figure 9. so20 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
l9826 block diagram doc id 7214 rev 10 5/19 1 block diagram figure 1.block diagram .#3 3$) #, + 3$ / ./ . /5 4 /5 4 /5 4 /5 4 /5 4 /5 4 /5 4 /5 4 '.$ $iag $iag .2 %3 1 #( $iag #( $iag 1 1 1 #( $iag 1 #( #( #( #( ./. $iag $iag 1 $iag 1 $iag 1 1 #( $iag &ault,atch 1 2e set 3hift2egister /utput,atch 30) )n terface 2 3 ,atch$river 2eset 5ndervoltage 2%3%4 3 2 ,atch$river 1 1 1 1 1 1 $iag $iag $ia g $ia g $ia g $ia g 6 ## 6 ## 6 ## 6 ## 6 ## 6 ## 6 ## 6 $' ) /, ) /, 6 $' /vertemperature$etection '.$ '!0'03
pins description l9826 6/19 doc id 7214 rev 10 2 pins description figure 2. connection diagram (top view) table 2. pin description n pin description 1 out 6 output 6 2 out 1 output 1 3 nres asynchronous reset 4 ncs chip select (active low) 5 gnd device ground 6 gnd device ground 7 non1 control input 1 8 sdo serial data output 9 out 8 output 8 10 out 3 output 3 11 out 5 output 5 12 out 2 output 2 13 sdi serial data input 14 clk serial clock 15 gnd device ground 16 gnd device ground 17 non2 control input 2 18 v cc supply voltage 19 out 7 output 7 20 out 4 output 4 /54 /54 n2%3 .#3 '.$ ./. '.$ 3$/ /54 /54 3$) #,+ '.$ '.$ ./. 6cc /54 /54 /54 /54 '!0'03
l9826 electrical specifications doc id 7214 rev 10 7/19 3 electrical specifications 3.1 absolute maximum ratings 3.2 thermal data table 3. absolute maximum ratings for voltages and currents applied externally to the device symbol parameter test condition min. typ. max. unit v cc supply voltage - -0.3 - 7 v inputs and data lines (nonx, ncs, clk, sdi, nres) v in voltage (nonx, ncs, clk, sdi, nres) -0.3 - 7 v i in protection diodes current (1) t ? 1ms -20 - 20 ma outputs (out1 ... out8) v outc continuous output voltage - -0.7 - 45 v i out output current (2) --2- 1.0a e outcl output clamp energy i out ? 150ma - - 10 mj 1. all inputs are protected against esd accordi ng to mil 883c; tested with hbm at 2 kv. it corresponds to a dissipated energy e ? 0.2 mj. 2. transient pulses in accordance to din40839 part 1, 3 and iso 7637 part 1, 3. table 4. absolute maximum ratings for currents determined within the device symbol parameter test condition min. typ. max. unit outputs (out1 ... out8) i out output current (out1, out2) - - - i lim a output current (out3 ... out8) - - - i scb a ? i out1 i = 1-8 total average-current all outputs (1) t amb = 60c 2.0 - - a 1. when operating the device with short circuit 1ch and 2ch outputs at the same time, damage due to electrical overstress might occur. table 5. thermal data symbol parameter test condition min. typ. max. unit thermal shutdown t jsc thermal shutdown threshold - 150 165 - c thermal resistance r thj a-one single output (junction ambient) - - - 90 c/w r thj a-all all outputs (junction ambient) - - - 75 c/w r th j-pin junction to pin - - - 18 c/w
electrical specifications l9826 8/19 doc id 7214 rev 10 3.3 electrical characteristics refer to 4.5 v ? v cc ? 5.5 v; -40 c ? t j ?? 150 c; unless otherwise specified. table 6. electrical characteristics symbol parameter test condition min. typ. max. unit supply voltage i ccstb standby current without load (nres = low) - - 70 ? a i ccopm operating mode i out1 ... 8 = 500 ma spi - clk = 3 mhz ncs = low sdo no load --5ma ? i cc ? i cc during reverse output current i out = -2 a - - 100 ma v ddres undervoltage reset reset of all registers and disable of all outputs 3-4v inputs (nonx. ncs, clk, sdi, nres) v inl low level - -0.3 - 0.2v cc v v inh high level - 0.7v cc - v cc +0,3 v v hyst hysteresis voltage - 0.85 - - v i in input current nonx, ncs, clk, sdi v in = v cc --10 ? a nres (v in = 0v) -10 - - ? a r in pull-up resistance (nonx, ncs, clk, sdi) pull-down resistance (nres) 50 - 250 k ? c in input capacitance guaranteed by design - - 10 pf serial data outputs v sdoh high output level i sdo = -4ma v cc -0.4 - - v v sdol low output level i sdo = 3,2ma - 0.4 v i sdol tristate leakage cu rrent ncs = high; 0v ? v sdo ? v cc -10 - 10 ? a c sdo output capacitance f sdo = 300 khz, guaranteed by design - - 10 pf outputs out 1 ... 8 i outl1 - 8 leakage current outx = off; v outx = 25 v; v cc = 5 v --100 ? a outx = off; v outx = 16 v; v cc = 5 v --100 ? a outx = off; v outx = 16 v; v cc = 1 v --10 ? a
l9826 electrical specifications doc id 7214 rev 10 9/19 v clp output clamp voltage 1 ma ? i clp ? i outp ; i test = 10 ma with correlation 45 - 62 v r dson on resistance out 1 ... 8 i out = 250 ma; t j = +150 c - - 3.0 ? c out output capacitance v out = 16 v; f = 1 mhz guaranteed by design --300pf outputs short circuit protection i sbc overcurrent shutoff threshold out3 ... out8 0.45 - 1.1 a i lim short circuit current limitation out1; out2 0.5 - 1.1 a t scb delay shutdown - 0.2 3,0 12 ? s diagnostics v dg diagnostic threshold voltage - 0.32 v cc - 0.4v cc v i ol open load detection sink current v out = v dg 20 - 100 ? a t df diagnostic detection filter time for output 1 & 2 on each diagnostic condition 15 - 50 ? s outputs timing t don1 turn on delay of out 1 and 2 non 1, 2 = 50% to v out = 0,9v bat ncs = 50% to v out = 0,9v bat (v bat = 16v, r l = 500 ? ) --5 ? s t don2 turn on delay of out 3 to 8 ncs = 50% to v out = 0,9v bat (v bat = 16v, r l = 500 ? ) --10 ? s t doff turn off delay of out 1 to 8 ncs = 50% to v out = 0,1v bat non 1, 2 = 50% to v out = 0,1v bat (v bat = 16v, r l = 500 ? ) --10 ? s du on1/dt turn on voltage slew-rate for output 3 to 8; 90% to 30% of v bat ; r l = 500 ? ; v bat = 16v 0.7 - 3.5 v/ ? s du on2/dt turn on voltage slew-rate for output 1 and 2; 90% to 30% of v bat ; r l = 500 ? ; v bat = 16v 2-10v/ ? s du off1/dt turn off voltage slew-rate for output 1 to 8; 30% to 90% of v bat ; r l = 500 ? ; v bat = 16v 2-10v/ ? s du off2/dt turn off voltage slew-rate for output 1 to 8; 30% to 80% of v bat ; r l = 500 ? ; v bat = 0.9 v clp 2-15v/ ? s serial diagnostic link (loa d capacitor at sdo = 100 pf) f clk clock frequency 50 % duty cycle - - 3 mhz t clh minimum time clk = high - 160 - - ns t cll minimum time clk = low - 160 - - ns t pcld propagation delay clk to data at sdo valid 4.9 v ? v cc ? 5.1v - - 100 ns table 6. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
electrical specifications l9826 10/19 doc id 7214 rev 10 t csdv ncs = low to data at sdo active ---100ns t sclch clk low before ncs low setup time clk to ncs change h/l 100 - - ns t hclcl clk change l/h after ncs = low -100--ns t scld sdi input setup time clk change h/l after sdi data valid 20 - - ns t hcld sdi input hold time sdi data hold after clk change h/l - - 20 ns t sclcl clk low before ncs high - 150 - - ns t hclch clk high after ncs high - 150 - - ns t pchdz ncs l/h to output data float - - - 100 ns - ncs pulse filter time multiple of 8 clk cycles inside ncs period ---- table 6. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
l9826 application information doc id 7214 rev 10 11/19 4 application information the typical application diagram is shown in figure 3 . figure 3. typical application circuit diagram for higher current capability th e two outputs of t he same kind can be paralleled and the maximum flyback energy should not exceed the limit for a single output. the circuit immunity at output transients have been verified during the characterization with test pulses 1, 2, 3a and 3b, din40839 or iso7637 part 3. the test pulses are coupled to the outputs with 200 pf series capacitor and all the outputs are able to withstand to test pulses without damage. the load applied was in the range of 30 to 100 ohm for the resistive part and 0 to 600 mh for the inductive one. .#3 #,/#+ 3$) 3$/ .2%3 ## 6 "!4 6 2,loads ?0 , , 6/,4!'% 2%'5,!4/2 .#3 3$) #,+ 3$/ ./. /54 /54 /54 /54 /54 /54 /54 /54 '.$ $iag $iag n2%3 1 #( $i ag #( $i ag 1 1 1 #( $iag 1 #( #( #( #( ./. $i ag $iag 1 $iag 1 $iag 1 1 #( $i ag &ault,atch 1 2eset 3hift2egister /utput,atch 30) )nterface 2 3 ,atch$river 2eset 5ndervoltage 2%3%4 3 2 ,atch$river 1 1 1 1 1 1 $iag $iag $iag $iag $iag $iag 6 ## 6 ## 6 ## '.$ 6 ## 6 ## 6 ## 6 ## 6 $' ) /, ) /, 6 $' /vertemperature$etection '!0'03
functional description l9826 12/19 doc id 7214 rev 10 5 functional description 5.1 general the l9826 is an 8-channel low-side driver assembled in so20 package. its 8-bit spi serial interface is designed to control all the outp uts and to provide their diagnosis. channels 1 and 2 are controlled either via spi or via parallel through the inputs pins non1 and non2. diagnostic recognizes operative fault conditions: open load, short circuits to gnd or to vb and overcurrent.thermal shutdown for outputs 1 and 2 is available as well the output voltage clamp which is essential in case of working with inductive loads. the reset feature is an or function of the external reset nres and the internal reset generate during the undervoltage condition 5.2 output stage control 5.2.1 via parallel, onl y for output 1 and 2 this is valid only for outputs 1 and 2 whic h are controlled through the dedicated inputs non1 and non2 (both active low) which ar e internally configured as pull-up (see figure 3 ). this is to guarantee that the outputs are off in case of inputs open. a further feature is the possibility to drive these outputs through a pwm signal independently by spi commands. reset signal is common for all the eight channels and it is active low. after an external reset condition (that means nres pin switched from low to high) to drive outputs 1 and 2 through the parallel input (non1 and non2) it is nece ssary to disable the parallel input itself (non1, non2 high) and then subsequently to drive the outputs 1 and 2 at the logic state desiderated through non1 and non2. the duration of the command (t) as reported in the figure 4 should be at less in the order of 100 nsecond. in the next figure 4 is shown this behavior and in the next ta b l e 7 is summarized the scenario of parallel/series commands. figure 4. parallel control for output 1 and 2 (example for power-on) table 7. outputs control tables outputs 1, 2: outputs 3 to 8: non1, 2 1 0 0 1 - - - spi-bit 1, 2 0 0 1 1 spi-bit 3 ... 8 0 1 output 1, 2 off on on on output 3 ... 8 off on 2esetoff 2eseton !nyvalues on 4 .2%3 ./.or /54or '!0'03
l9826 functional description doc id 7214 rev 10 13/19 5.2.2 via 8-bit spi for all the outputs control data are transmitted to sdi through a microcontroller in configuration master. the device is selected when ncs signal is low. the 8-bit command data are transmitted into l9826 shift regi sters every clk falling edge (see figure 6 for spi signals timing). the ncs rising edge latches the new data from the shift register to the driver and the output are driven following the commands just sent. the digital filter between ncs and the output latch ensures that the data are transferred only after 8 clk cycles or multiple of 8 clk cycles since the last ncs falling edge. the ncs changes only at low clk. figure 5 shows the control register structure and in the detail its cont rol-bit, while in the ta bl e 7 are summarized the controls outputs via spi or dedicated input pins (non1 and non2). figure 5. output control register structure figure 6. timing of the serial interface '!0'03 1 1 1 1 1 1 1 1 -3" ,3" #ontrol bitoutput #ontrol bitoutput #ontrol bitoutput #ontrol bitoutput #ontrol bitoutput #ontrol bitoutput #ontrol bitoutput #ontrol bitoutput '!0'03 .#3 #,+ 3$) 3$/ tsclch thclcl tclh tcll tsclcl thclch tcsdv tpcld tpchdz notdefined $ $ tscld thcld $ $ $
functional description l9826 14/19 doc id 7214 rev 10 5.3 output stage diagnostics all the outputs voltage are compared with the diagnostic threshold (0.38 typ vcc) and this information is transferred in dedicated fault latches which are cleared when the ncs reaches the state low. afterward the latch stores the status bit and the first reading after the error might be wrong. the second one is considered right. the next figure 7 and 8 show the diagnostic bits read out on sdo and their organization into the dedicated registers. when ncs is low the data contained in the shift register are transferred to sdo output every clk rising edge. figure 7. the pulse diagram to read the outputs status register figure 8. the structure of the outputs status register '!0'03 .#3 #,+ 3$) 3$/ -3" ,3" -3 " ,3" '!0'03 $iag $iag $iag $iag $iag $iag $iag $iag -3" ,3" $iagnostic bitoutput $iagnostic bitoutput $iagnostic bitoutput $iagnostic bitoutput $iagnostic bitoutput $iagnostic bitoutput $iagnostic bitoutput $iagnostic bitoutput
l9826 functional description doc id 7214 rev 10 15/19 5.3.1 diagnostic on outputs 1 and 2 controlled via non1/non2 fault condition (1) "output shorted to vbat" the output has been previously switched-on and its voltage exceeds the diagnostics threshold. it operates in current regulation mode or it is switched-off if thermal shutdown threshold (t jsc ) is reached. the status bit is low. fault condition (2) "open load" or "output shorted to gnd" the output is switched-off and its voltage drops below the diagnostics threshold because the load current is lower than the output diagnostic current source. the diagnostic bit is low. 5.3.2 diagnostic on outputs 1 to 8 controlled via spi fault condition (1) "output shorted to vbat" the output was previously switched-on, its voltage exceeds the diagnostic threshold and the result is that the output is switched-off. the diagnostic bit is high. fault condition (2) "open load" or "output shorted to gnd" it is the same behavior explained for the outputs 1 and 2 (see paragraph 5.3.1), at ncs falling edge the output stat us data are transferred to the shift register. load diagnostic: when the output is in off condition a typical diagnostic current of 60 a is sinked. table 8. diagnostic table for outputs 1 and 2 in parallel controlled mode output 1, 2 output-volta ge status-bit output-mode off > dg-threshold high correct operation off < dg-threshold low fault condition 2) on < dg-threshold high correct operation on > dg-threshold low fault condition 1) table 9. diagnostic table for outputs 1 to 8 in spi controlled mode output 1 ... 8 output-volta ge status-bit output-mode off > dg-threshold high correct operation off < dg-threshold low fault condition 2) on < dg-threshold low correct operation on > dg-threshold high fault condition 1)
functional description l9826 16/19 doc id 7214 rev 10 5.4 protections 5.4.1 flyback current turning off the low side driver with an inductive load, its output voltage rises due to the inductor that tries to drive current. this voltage is internally clamped by the flyback circuit at v cpl value, typical 50v 5.4.2 current regulat ion mode outputs 1 and 2 outputs 1 and 2 which are particularly dedicated for loads with inrush current (as lamps). when the channel is switched on and the current through the load exceeds the short circuit limit value ( ilim ) for at least t df time, the corresponding output goes in current regulation mode. the output current is determinated by the output characteristic and its voltage depends on load resistance. in this mode, high power is dissipated in the output stage and its temperature increases rapidly. when the output stage temperature exceeds the thermal shutdown (t jsc ), the overload latch is set and the corresponding output is switched off. 5.4.3 short circuits outputs 3 to 8 outputs 3 to 8 which are dedicated for loads without inrush currents. when the output current exceeds the short circuit threshold (i sbc ) for at least t scb time, the corresponding output is switched-off immediately and in the same time, the relative latch store the overload status.
l9826 package information doc id 7214 rev 10 17/19 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 9. so20 mechanical data and package dimensions '!0'03 /54,).%!.$ -%#(!.)#!,$!4! $)- mm inch -). 490 -!8 -). 490 -!8 ! ! " # $ % e ( h , k ?plq?pd[ ddd h$vdimensiondoesnotincludemoldflashprotusionsorga te burrs-oldflashprotusionsorgateburrsshallnotexceed mmperside 3/ $
revision history l9826 18/19 doc id 7214 rev 10 7 revision history table 10. document revision history date revision changes 22-apr-2004 7 initial release in edocs 26-jul-2005 8 document reformatted. modify value r on in the ?features?. 08-feb-2011 9 updated features and description on page 1 . updated table 1: device summary on page 1 . updated figure 3: typical application circuit diagram . reworked the content of the section 5: functional description . 19-sep-2013 10 updated disclaimer.
l9826 doc id 7214 rev 10 19/19 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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